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468 lines
18 KiB
468 lines
18 KiB
/* This file is a part of MIR project.
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Copyright (C) 2018-2020 Vladimir Makarov <vmakarov.gcc@gmail.com>.
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*/
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// _MIR_get_thunk, _MIR_redirect_thunk, _MIR_get_interp_shim, _MIR_get_ff_call, _MIR_get_wrapper
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#define VA_LIST_IS_ARRAY_P 1 /* one element which is a pointer to args */
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#define FUNC_DESC_LEN 24
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static void ppc64_push_func_desc (MIR_context_t ctx);
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void (*ppc64_func_desc) (MIR_context_t ctx) = ppc64_push_func_desc;
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static void ppc64_push_func_desc (MIR_context_t ctx) {
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VARR_TRUNC (uint8_t, machine_insns, 0);
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for (int i = 0; i < FUNC_DESC_LEN; i++)
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VARR_PUSH (uint8_t, machine_insns, ((uint8_t *) ppc64_func_desc)[i]);
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}
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static void ppc64_redirect_func_desc (MIR_context_t ctx, void *desc, void *to) {
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mir_assert (((uint64_t) desc & 0x3) == 0 && ((uint64_t) to & 0x3) == 0); /* alignment */
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_MIR_change_code (ctx, desc, (uint8_t *) &to, sizeof (to));
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}
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static void *ppc64_publish_func_and_redirect (MIR_context_t ctx) {
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void *res = _MIR_publish_code (ctx, VARR_ADDR (uint8_t, machine_insns),
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VARR_LENGTH (uint8_t, machine_insns));
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ppc64_redirect_func_desc (ctx, res, (uint8_t *) res + FUNC_DESC_LEN);
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return res;
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}
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static void push_insn (MIR_context_t ctx, uint32_t insn) {
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uint8_t *p = (uint8_t *) &insn;
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for (size_t i = 0; i < 4; i++) VARR_PUSH (uint8_t, machine_insns, p[i]);
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}
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static void push_insns (MIR_context_t ctx, const uint32_t *pat, size_t pat_len) {
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uint8_t *p = (uint8_t *) pat;
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for (size_t i = 0; i < pat_len; i++) VARR_PUSH (uint8_t, machine_insns, p[i]);
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}
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void *_MIR_get_bstart_builtin (MIR_context_t ctx) {
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static const uint32_t bstart_code[] = {
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0x7c230b78, /* mr 3,1 */
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0x4e800020, /* blr */
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};
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ppc64_push_func_desc (ctx);
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push_insns (ctx, bstart_code, sizeof (bstart_code));
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return ppc64_publish_func_and_redirect (ctx);
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}
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void *_MIR_get_bend_builtin (MIR_context_t ctx) {
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static const uint32_t bend_code[] = {
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0xe8010000, /* ld r0,0(r1) */
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0xf8030000, /* std r0,0(r3) */
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0xe8010028, /* ld r0,40(r1) */
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0xf8030028, /* std r0,40(r3) */
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0x7c611b78, /* mr r1,r3 */
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0x4e800020, /* blr */
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};
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ppc64_push_func_desc (ctx);
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push_insns (ctx, bend_code, sizeof (bend_code));
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return ppc64_publish_func_and_redirect (ctx);
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}
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void *_MIR_get_thunk (MIR_context_t ctx) { /* emit 3 doublewords for func descriptor: */
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ppc64_push_func_desc (ctx);
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return ppc64_publish_func_and_redirect (ctx);
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}
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void _MIR_redirect_thunk (MIR_context_t ctx, void *thunk, void *to) {
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ppc64_redirect_func_desc (ctx, thunk, to);
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}
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struct ppc64_va_list {
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uint64_t *arg_area;
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};
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void *va_arg_builtin (void *p, uint64_t t) {
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struct ppc64_va_list *va = p;
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MIR_type_t type = t;
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int fp_p = type == MIR_T_F || type == MIR_T_D;
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void *a = va->arg_area;
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if (type == MIR_T_F || type == MIR_T_I32) {
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a = (char *) a + 4; /* 2nd word of doubleword */
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va->arg_area = (uint64_t *) ((char *) a + 4);
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} else if (type == MIR_T_LD) {
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va->arg_area += 2;
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} else {
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va->arg_area++;
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}
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return a;
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}
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void va_start_interp_builtin (MIR_context_t ctx, void *p, void *a) {
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struct ppc64_va_list **va = p;
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va_list *vap = a;
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assert (sizeof (struct ppc64_va_list) == sizeof (va_list));
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*va = (struct ppc64_va_list *) vap;
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}
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void va_end_interp_builtin (MIR_context_t ctx, void *p) {}
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static void ppc64_gen_mov (MIR_context_t ctx, unsigned to, unsigned from) {
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/* or to,from,from: */
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push_insn (ctx, (31 << 26) | (444 << 1) | (from << 21) | (to << 16) | (from << 11));
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}
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static void ppc64_gen_addi (MIR_context_t ctx, unsigned rt_reg, unsigned ra_reg, int disp) {
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push_insn (ctx, (14 << 26) | (rt_reg << 21) | (ra_reg << 16) | (disp & 0xffff));
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}
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static void ppc64_gen_ld (MIR_context_t ctx, unsigned to, unsigned base, int disp,
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MIR_type_t type) {
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int single_p = type == MIR_T_F;
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int double_p = type == MIR_T_D || type == MIR_T_LD;
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/* (ld | lf[sd]) to, disp(base): */
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assert (base != 0 && base < 32 && to < 32 && (single_p || double_p || (disp & 0x3) == 0));
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push_insn (ctx, ((single_p ? 48 : double_p ? 50 : 58) << 26) | (to << 21) | (base << 16)
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| (disp & 0xffff));
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}
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static void ppc64_gen_st (MIR_context_t ctx, unsigned from, unsigned base, int disp,
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MIR_type_t type) {
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int single_p = type == MIR_T_F;
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int double_p = type == MIR_T_D || type == MIR_T_LD;
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/* std|stf[sd] from, disp(base): */
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assert (base != 0 && base < 32 && from < 32 && (single_p || double_p || (disp & 0x3) == 0));
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push_insn (ctx, ((single_p ? 52 : double_p ? 54 : 62) << 26) | (from << 21) | (base << 16)
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| (disp & 0xffff));
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}
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static void ppc64_gen_stdu (MIR_context_t ctx, int disp) {
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assert ((disp & 0x3) == 0);
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push_insn (ctx, 0xf8210001 | disp & 0xfffc); /* stdu 1, disp (1) */
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}
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static void ppc64_gen_address (MIR_context_t ctx, unsigned int reg, void *p) {
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uint64_t a = (uint64_t) p;
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if ((a >> 32) == 0) {
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if (((a >> 31) & 1) == 0) { /* lis r,0,Z2 */
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push_insn (ctx, (15 << 26) | (reg << 21) | (0 << 16) | (a >> 16) & 0xffff);
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} else { /* xor r,r,r; oris r,r,Z2 */
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push_insn (ctx, (31 << 26) | (316 << 1) | (reg << 21) | (reg << 16) | (reg << 11));
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push_insn (ctx, (25 << 26) | (reg << 21) | (reg << 16) | (a >> 16) & 0xffff);
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}
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} else {
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/* lis r,0,Z0; ori r,r,Z1; rldicr r,r,32,31; oris r,r,Z2; ori r,r,Z3: */
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push_insn (ctx, (15 << 26) | (reg << 21) | (0 << 16) | (a >> 48));
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push_insn (ctx, (24 << 26) | (reg << 21) | (reg << 16) | (a >> 32) & 0xffff);
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push_insn (ctx, (30 << 26) | (reg << 21) | (reg << 16) | 0x07c6);
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push_insn (ctx, (25 << 26) | (reg << 21) | (reg << 16) | (a >> 16) & 0xffff);
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}
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push_insn (ctx, (24 << 26) | (reg << 21) | (reg << 16) | a & 0xffff);
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}
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static void ppc64_gen_jump (MIR_context_t ctx, unsigned int reg, int call_p) {
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ppc64_gen_ld (ctx, 0, reg, 0, MIR_T_I64); /* 0 = func addr */
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ppc64_gen_ld (ctx, 2, reg, 8, MIR_T_I64); /* r2 = TOC */
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push_insn (ctx, (31 << 26) | (467 << 1) | (0 << 21) | (9 << 16)); /* mctr 0 */
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push_insn (ctx, (19 << 26) | (528 << 1) | (20 << 21) | (call_p ? 1 : 0)); /* bcctr[l] */
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}
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/* Generation: fun (fun_addr, res_arg_addresses):
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save lr (r1 + 16); allocate and form minimal stack frame (with necessary param area); save r14;
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r12=fun_addr (r3); r14 = res_arg_addresses (r4);
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r0=mem[r14,<args_offset>]; (arg_reg=mem[r0] or r0=mem[r0];mem[r1,r1_offset]=r0) ...
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if func is vararg: put fp args also in gp regs
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call *r12;
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r0=mem[r14,<offset>]; res_reg=mem[r0]; ...
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restore r14, r1, lr; return. */
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void *_MIR_get_ff_call (MIR_context_t ctx, size_t nres, MIR_type_t *res_types, size_t nargs,
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MIR_type_t *arg_types, int vararg_p) {
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static uint32_t start_pattern[] = {
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0x7c0802a6, /* mflr r0 */
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0xf8010010, /* std r0,16(r1) */
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};
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static uint32_t finish_pattern[] = {
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0xe8010010, /* ld r0,16(r1) */
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0x7c0803a6, /* mtlr r0 */
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0x4e800020, /* blr */
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};
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MIR_type_t type;
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int n_gpregs = 0, n_fpregs = 0, res_reg = 14, frame_size, disp, param_offset, param_size = 0;
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ppc64_push_func_desc (ctx);
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for (uint32_t i = 0; i < nargs; i++) param_size += arg_types[i] == MIR_T_LD ? 16 : 8;
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if (param_size < 64) param_size = 64;
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frame_size = 48 + param_size + 8; /* +local var to save res_reg */
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if (frame_size % 8 != 0) frame_size += 8; /* align */
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ppc64_gen_st (ctx, 2, 1, 40, MIR_T_I64);
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push_insns (ctx, start_pattern, sizeof (start_pattern));
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ppc64_gen_stdu (ctx, -frame_size);
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ppc64_gen_st (ctx, res_reg, 1, 48 + param_size, MIR_T_I64); /* save res_reg */
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mir_assert (sizeof (long double) == 16);
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ppc64_gen_mov (ctx, res_reg, 4); /* results & args */
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ppc64_gen_mov (ctx, 12, 3); /* func addr */
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n_gpregs = n_fpregs = 0;
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param_offset = nres * 16; /* args start */
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disp = 48; /* param area start */
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for (uint32_t i = 0; i < nargs; i++) { /* load args: */
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type = arg_types[i];
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if ((type == MIR_T_F || type == MIR_T_D || type == MIR_T_LD) && n_fpregs < 13) {
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ppc64_gen_ld (ctx, 1 + n_fpregs, res_reg, param_offset, type);
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if (vararg_p) {
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if (n_gpregs >= 8) {
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ppc64_gen_st (ctx, 1 + n_fpregs, 1, disp, MIR_T_D);
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} else { /* load gp reg to */
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ppc64_gen_st (ctx, 1 + n_fpregs, 1, -8, MIR_T_D);
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ppc64_gen_ld (ctx, 3 + n_gpregs, 1, -8, MIR_T_I64);
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}
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}
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n_fpregs++;
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if (type == MIR_T_LD) {
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if (n_fpregs < 13) {
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ppc64_gen_ld (ctx, 1 + n_fpregs, res_reg, param_offset + 8, type);
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if (vararg_p) {
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if (n_gpregs + 1 >= 8) {
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ppc64_gen_st (ctx, 1 + n_fpregs, 1, disp + 8, MIR_T_D);
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} else { /* load gp reg to */
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ppc64_gen_st (ctx, 1 + n_fpregs, 1, -8, MIR_T_D);
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ppc64_gen_ld (ctx, 4 + n_gpregs, 1, -8, MIR_T_I64);
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}
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}
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n_fpregs++;
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} else {
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ppc64_gen_ld (ctx, 0, res_reg, param_offset + 8, type);
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ppc64_gen_st (ctx, 0, 1, disp + 8, MIR_T_D);
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}
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}
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} else if (n_gpregs < 8) {
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ppc64_gen_ld (ctx, n_gpregs + 3, res_reg, param_offset, MIR_T_I64);
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} else if (type == MIR_T_F || type == MIR_T_D || type == MIR_T_LD) {
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ppc64_gen_ld (ctx, 0, res_reg, param_offset, type);
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ppc64_gen_st (ctx, 0, 1, disp, MIR_T_D);
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if (type == MIR_T_LD) {
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ppc64_gen_ld (ctx, 0, res_reg, param_offset + 8, type);
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ppc64_gen_st (ctx, 0, 1, disp + 8, MIR_T_D);
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}
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} else {
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ppc64_gen_ld (ctx, 0, res_reg, param_offset, MIR_T_I64);
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ppc64_gen_st (ctx, 0, 1, disp, MIR_T_I64);
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}
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disp += type == MIR_T_LD ? 16 : 8;
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param_offset += 16;
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n_gpregs += type == MIR_T_LD ? 2 : 1;
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}
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ppc64_gen_jump (ctx, 12, TRUE); /* call func_addr */
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n_gpregs = n_fpregs = 0;
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disp = 0;
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for (uint32_t i = 0; i < nres; i++) {
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type = res_types[i];
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if ((type == MIR_T_F || type == MIR_T_D || type == MIR_T_LD) && n_fpregs < 4) {
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ppc64_gen_st (ctx, n_fpregs + 1, res_reg, disp, type);
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n_fpregs++;
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if (type == MIR_T_LD) {
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if (n_fpregs >= 4)
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(*error_func) (MIR_ret_error, "ppc64 can not handle this combination of return values");
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ppc64_gen_st (ctx, n_fpregs + 1, res_reg, disp + 8, type);
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n_fpregs++;
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}
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} else if (n_gpregs < 1) { // just one gp reg
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ppc64_gen_st (ctx, n_gpregs + 3, res_reg, disp, MIR_T_I64);
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n_gpregs++;
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} else {
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(*error_func) (MIR_ret_error, "ppc64 can not handle this combination of return values");
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}
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disp += 16;
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}
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ppc64_gen_ld (ctx, res_reg, 1, 48 + param_size, MIR_T_I64); /* restore res_reg */
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ppc64_gen_addi (ctx, 1, 1, frame_size);
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push_insns (ctx, finish_pattern, sizeof (finish_pattern));
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return ppc64_publish_func_and_redirect (ctx);
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}
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/* Transform C call to call of void handler (MIR_context_t ctx, MIR_item_t func_item,
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va_list va, MIR_val_t *results):
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Brief: put all C call args to local vars (or if va_arg do nothing); save lr (r1+16), r14;
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allocate and form minimal shim stack frame (param area = 8 * 8);
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call handler with args; move results(r14) to return regs; restore lr,r14,r1; return */
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void *_MIR_get_interp_shim (MIR_context_t ctx, MIR_item_t func_item, void *handler) {
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MIR_func_t func = func_item->u.func;
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uint32_t nres = func->nres, nargs = func->nargs;
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int vararg_p = func->vararg_p;
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MIR_type_t type, *res_types = func->res_types;
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MIR_var_t *arg_vars = VARR_ADDR (MIR_var_t, func->vars);
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int disp, size, frame_size, local_var_size, param_offset, va_reg = 11, caller_r1 = 12,
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res_reg = 14;
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int n_gpregs, n_fpregs;
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static uint32_t start_pattern[] = {
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0x7c0802a6, /* mflr r0 */
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0xf8010010, /* std r0,16(r1) */
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};
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static uint32_t finish_pattern[] = {
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0xe8010010, /* ld r0,16(r1) */
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0x7c0803a6, /* mtlr r0 */
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0x4e800020, /* blr */
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};
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static uint32_t save_gp_regs_pattern[] = {
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0xf8610030, /* std r3,48(r1) */
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0xf8810038, /* std r4,56(r1) */
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0xf8a10040, /* std r5,64(r1) */
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0xf8c10048, /* std r6,72(r1) */
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0xf8e10050, /* std r7,80(r1) */
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0xf9010058, /* std r8,88(r1) */
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0xf9210060, /* std r9,96(r1) */
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0xf9410068, /* std r10,104(r1) */
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};
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VARR_TRUNC (uint8_t, machine_insns, 0);
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frame_size = 112; /* 6(frame start) + 8(param area) */
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local_var_size = nres * 16 + 8; /* saved r14, results */
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if (vararg_p) {
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push_insns (ctx, save_gp_regs_pattern, sizeof (save_gp_regs_pattern));
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ppc64_gen_addi (ctx, va_reg, 1, 48);
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} else {
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ppc64_gen_mov (ctx, caller_r1, 1); /* caller frame r1 */
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for (uint32_t i = 0; i < nargs; i++) {
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type = arg_vars[i].type;
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local_var_size += type == MIR_T_LD ? 16 : 8;
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}
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}
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frame_size += local_var_size;
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if (frame_size % 8 != 0) frame_size += 8; /* align */
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push_insns (ctx, start_pattern, sizeof (start_pattern));
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ppc64_gen_stdu (ctx, -frame_size);
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ppc64_gen_st (ctx, res_reg, 1, 48 + 64, MIR_T_I64); /* save res_reg */
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if (!vararg_p) { /* save args in local vars: */
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disp = 112 + nres * 16 + 8; /* 48 + 64 + nres * 16 + 8: start of local vars to keep args */
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ppc64_gen_addi (ctx, va_reg, 1, disp);
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param_offset = 48;
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n_gpregs = n_fpregs = 0;
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for (uint32_t i = 0; i < nargs; i++) {
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type = arg_vars[i].type;
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if ((type == MIR_T_F || type == MIR_T_D || type == MIR_T_LD) && n_fpregs < 13) {
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ppc64_gen_st (ctx, n_fpregs + 1, 1, disp, MIR_T_D);
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n_fpregs++;
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if (type == MIR_T_LD) {
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if (n_fpregs < 13) {
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ppc64_gen_st (ctx, n_fpregs + 1, 1, disp + 8, MIR_T_D);
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n_fpregs++;
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} else {
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ppc64_gen_ld (ctx, 0, caller_r1, param_offset + 8, MIR_T_D);
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ppc64_gen_st (ctx, 0, 1, disp + 8, MIR_T_D);
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}
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}
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} else if (n_gpregs < 8) {
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ppc64_gen_st (ctx, n_gpregs + 3, 1, disp, MIR_T_I64);
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} else if (type == MIR_T_F || type == MIR_T_D || type == MIR_T_LD) {
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ppc64_gen_ld (ctx, 0, caller_r1, param_offset + (type == MIR_T_F ? 4 : 0), type);
|
|
ppc64_gen_st (ctx, 0, 1, disp, MIR_T_D);
|
|
if (type == MIR_T_LD) {
|
|
ppc64_gen_ld (ctx, 0, caller_r1, param_offset + 8, MIR_T_D);
|
|
ppc64_gen_st (ctx, 0, 1, disp + 8, MIR_T_D);
|
|
}
|
|
} else {
|
|
ppc64_gen_ld (ctx, 0, caller_r1, param_offset, MIR_T_I64);
|
|
ppc64_gen_st (ctx, 0, 1, disp, MIR_T_I64);
|
|
}
|
|
size = type == MIR_T_LD ? 16 : 8;
|
|
disp += size;
|
|
param_offset += size;
|
|
n_gpregs += type == MIR_T_LD ? 2 : 1;
|
|
}
|
|
}
|
|
ppc64_gen_addi (ctx, res_reg, 1, 64 + 48 + 8);
|
|
ppc64_gen_address (ctx, 3, ctx);
|
|
ppc64_gen_address (ctx, 4, func_item);
|
|
ppc64_gen_mov (ctx, 5, va_reg);
|
|
ppc64_gen_mov (ctx, 6, res_reg);
|
|
ppc64_gen_address (ctx, 7, handler);
|
|
ppc64_gen_jump (ctx, 7, TRUE);
|
|
disp = n_gpregs = n_fpregs = 0;
|
|
for (uint32_t i = 0; i < nres; i++) {
|
|
type = res_types[i];
|
|
if ((type == MIR_T_F || type == MIR_T_D || type == MIR_T_LD) && n_fpregs < 4) {
|
|
ppc64_gen_ld (ctx, n_fpregs + 1, res_reg, disp, type);
|
|
n_fpregs++;
|
|
if (type == MIR_T_LD) {
|
|
if (n_fpregs >= 4)
|
|
(*error_func) (MIR_ret_error, "ppc64 can not handle this combination of return values");
|
|
ppc64_gen_ld (ctx, n_fpregs + 1, res_reg, disp + 8, type);
|
|
n_fpregs++;
|
|
}
|
|
} else if (n_gpregs < 1) { // just one gp reg
|
|
ppc64_gen_ld (ctx, n_gpregs + 3, res_reg, disp, MIR_T_I64);
|
|
n_gpregs++;
|
|
} else {
|
|
(*error_func) (MIR_ret_error, "ppc64 can not handle this combination of return values");
|
|
}
|
|
disp += 16;
|
|
}
|
|
ppc64_gen_ld (ctx, res_reg, 1, 48 + 64, MIR_T_I64); /* restore res_reg */
|
|
ppc64_gen_addi (ctx, 1, 1, frame_size);
|
|
push_insns (ctx, finish_pattern, sizeof (finish_pattern));
|
|
return _MIR_publish_code (ctx, VARR_ADDR (uint8_t, machine_insns),
|
|
VARR_LENGTH (uint8_t, machine_insns));
|
|
}
|
|
|
|
/* Brief: save lr (r1+16); update r1, save all param regs (r1+112);
|
|
allocate and form minimal wrapper stack frame (param area = 8*8);
|
|
r3 = call hook_address (ctx, called_func);
|
|
restore params regs (r1+112), r1, lr (r1+16); ctr=r11; b *ctr */
|
|
void *_MIR_get_wrapper (MIR_context_t ctx, MIR_item_t called_func, void *hook_address) {
|
|
static uint32_t prologue[] = {
|
|
0x7c0802a6, /* mflr r0 */
|
|
0xf8010010, /* std r0,16(r1) */
|
|
0xf821fee9, /* stdu r1,-280(r1): 6(frame start) + 8(gp args) + 13(fp args) + 8(param area) */
|
|
0xf8610070, /* std r3,112(r1) */
|
|
0xf8810078, /* std r4,120(r1) */
|
|
0xf8a10080, /* std r5,128(r1) */
|
|
0xf8c10088, /* std r6,136(r1) */
|
|
0xf8e10090, /* std r7,144(r1) */
|
|
0xf9010098, /* std r8,152(r1) */
|
|
0xf92100a0, /* std r9,160(r1) */
|
|
0xf94100a8, /* std r10,168(r1) */
|
|
0xd82100b0, /* stfd f1,176(r1) */
|
|
0xd84100b8, /* stfd f2,184(r1) */
|
|
0xd86100c0, /* stfd f3,192(r1) */
|
|
0xd88100c8, /* stfd f4,200(r1) */
|
|
0xd8a100d0, /* stfd f5,208(r1) */
|
|
0xd8c100d8, /* stfd f6,216(r1) */
|
|
0xd8e100e0, /* stfd f7,224(r1) */
|
|
0xd90100e8, /* stfd f8,232(r1) */
|
|
0xd92100f0, /* stfd f9,240(r1) */
|
|
0xd94100f8, /* stfd f10,248(r1) */
|
|
0xd9610100, /* stfd f11,256(r1) */
|
|
0xd9810108, /* stfd f12,264(r1) */
|
|
0xd9a10110, /* stfd f13,272(r1) */
|
|
};
|
|
static uint32_t epilogue[] = {
|
|
0xe8610070, /* ld r3,112(r1) */
|
|
0xe8810078, /* ld r4,120(r1) */
|
|
0xe8a10080, /* ld r5,128(r1) */
|
|
0xe8c10088, /* ld r6,136(r1) */
|
|
0xe8e10090, /* ld r7,144(r1) */
|
|
0xe9010098, /* ld r8,152(r1) */
|
|
0xe92100a0, /* ld r9,160(r1) */
|
|
0xe94100a8, /* ld r10,168(r1) */
|
|
0xc82100b0, /* lfd f1,176(r1) */
|
|
0xc84100b8, /* lfd f2,184(r1) */
|
|
0xc86100c0, /* lfd f3,192(r1) */
|
|
0xc88100c8, /* lfd f4,200(r1) */
|
|
0xc8a100d0, /* lfd f5,208(r1) */
|
|
0xc8c100d8, /* lfd f6,216(r1) */
|
|
0xc8e100e0, /* lfd f7,224(r1) */
|
|
0xc90100e8, /* lfd f8,232(r1) */
|
|
0xc92100f0, /* lfd f9,240(r1) */
|
|
0xc94100f8, /* lfd f10,248(r1) */
|
|
0xc9610100, /* lfd f11,256(r1) */
|
|
0xc9810108, /* lfd f12,264(r1) */
|
|
0xc9a10110, /* lfd f13,272(r1) */
|
|
0x38210118, /* addi r1,r1,280 */
|
|
0xe8010010, /* ld r0,16(r1) */
|
|
0x7c0803a6, /* mtlr r0 */
|
|
};
|
|
|
|
VARR_TRUNC (uint8_t, machine_insns, 0);
|
|
push_insns (ctx, prologue, sizeof (prologue));
|
|
ppc64_gen_address (ctx, 3, ctx);
|
|
ppc64_gen_address (ctx, 4, called_func);
|
|
ppc64_gen_address (ctx, 5, hook_address);
|
|
ppc64_gen_jump (ctx, 5, TRUE);
|
|
ppc64_gen_mov (ctx, 11, 3);
|
|
push_insns (ctx, epilogue, sizeof (epilogue));
|
|
ppc64_gen_jump (ctx, 11, FALSE);
|
|
}
|