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@ -1,5 +1,5 @@
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/* This file is a part of MIR project.
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Copyright (C) 2020 Vladimir Makarov <vmakarov.gcc@gmail.com>.
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Copyright (C) 2020-2021 Vladimir Makarov <vmakarov.gcc@gmail.com>.
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*/
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// ??? More patterns (ult, ugt, ule, uge w/o branches, multi-insn combining).
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@ -766,9 +766,9 @@ static void target_machinize (gen_ctx_t gen_ctx) {
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}
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if ((nargs = get_builtin (gen_ctx, code, &proto_item, &func_import_item)) > 0) {
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if (code == MIR_VA_ARG || code == MIR_VA_BLOCK_ARG) {
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/* Use a builtin func call:
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mov func_reg, func ref; [mov reg3, type;] call proto, func_reg, res_reg, va_reg,
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reg3 */
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/* Use a builtin func call:
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mov func_reg, func ref; [mov reg3, type;] call proto, func_reg, res_reg, va_reg,
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reg3 */
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MIR_op_t ops[6], func_reg_op, reg_op3;
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MIR_op_t res_reg_op = insn->ops[0], va_reg_op = insn->ops[1], op3 = insn->ops[2];
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@ -779,18 +779,18 @@ static void target_machinize (gen_ctx_t gen_ctx) {
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next_insn = new_insn
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= MIR_new_insn (ctx, MIR_MOV, func_reg_op, MIR_new_ref_op (ctx, func_import_item));
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gen_add_insn_before (gen_ctx, insn, new_insn);
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if (code == MIR_VA_ARG) {
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new_insn = MIR_new_insn (ctx, MIR_MOV, reg_op3,
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MIR_new_int_op (ctx, (int64_t) op3.u.mem.type));
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op3 = reg_op3;
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gen_add_insn_before (gen_ctx, insn, new_insn);
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}
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if (code == MIR_VA_ARG) {
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new_insn
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= MIR_new_insn (ctx, MIR_MOV, reg_op3, MIR_new_int_op (ctx, (int64_t) op3.u.mem.type));
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op3 = reg_op3;
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gen_add_insn_before (gen_ctx, insn, new_insn);
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}
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ops[0] = MIR_new_ref_op (ctx, proto_item);
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ops[1] = func_reg_op;
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ops[2] = res_reg_op;
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ops[3] = va_reg_op;
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ops[4] = op3;
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if (code == MIR_VA_BLOCK_ARG) ops[5] = insn->ops[3];
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if (code == MIR_VA_BLOCK_ARG) ops[5] = insn->ops[3];
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new_insn = MIR_new_insn_arr (ctx, MIR_CALL, code == MIR_VA_ARG ? 5 : 6, ops);
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gen_add_insn_before (gen_ctx, insn, new_insn);
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gen_delete_insn (gen_ctx, insn);
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